Hi Chuck,

Analog IC multipliers are rather noisy themselves. Usually they involve 
a log amplifier, which is often a P-N junction biased to a rather low 
current level -- just the right combination for noise.

If you choose the carrier frequency high enough above the signal 
passband you should have enough difference to filter the spikes quite well.

Much of the noise is due to charge being injected through the gate 
capacitance of the switches, and one trick is to cancel the noise by 
injecting charge of the opposite polarity from an inverted signal.

Sometimes slowing the risetime of the switching signal helps. There is 
less current through the capacitances with slower risetimes. But the 
resultant noise has lower frequency content and may be harder to filter. 
And sometimes using faster switching risetimes is better, for the 
opposite reasons.

And as was mentioned, careful board layout can make all the difference 
in the world.

You might look at IC analog switches. They usually specify switching 
charge injection. Low charge injection often comes at the expense of 
speed and on resistance.

Hope this helps.

Karl


Chuck / Judy Burch wrote:
> 
> Here's a technical question about seismometer electronics.  What phase 
> sensitive detector design do you recommend for low noise?
> 
> I have built PSDs using an op amp and FET switches (the amp switches 
> between gain of +1 and -1).  Analog Technology and National Semi 
> describe these circuits in application notes.  And you can use a switch 
> with an instrumentation amp.  But these switches produce huge high 
> frequency noise pulses that are very difficult to shield out or filter out.
> 
> You could also use IC multipliers like the AD630 or a Gilbert cell 
> multiplier.  I have not tried either of these and wonder if they are 
> worth the cost and/or trouble of construction.
> 
> Any suggestions?
> 
> Thanks,
> 
> Chuck Burch
> 
> 
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